A multilayered wiring in a chip is required to be finer along with higher integration and miniaturization in a memory and the like, and it is expected that the most recent flash memory reaches a half pitch of 10 nm or less around 2020. On the other hand, resistivity is rapidly increasing along with the miniaturization due to an increase in inelastic scattering of a generally-used metal wiring of Cu or the like, and is reaching the limit of the material. To the contrary, it is reported that a nano-carbon material such as graphene or carbon nanotube (CNT) has a remarkably longer mean free path or higher mobility also in a finer area than the metals, which is expected as a next-generation fine wiring material. In particular, graphene may form a fine-width wiring in a lithography process well compatible with the existing LSI (large Scale Integration) process, and fine-width integrated wiring based on multilayered graphene by CVD (Chemical Vapor Deposition) is increasingly developed.
When a multilayered graphene itself is only thinned, the thinned multilayered graphene has high resistance, and is insufficient to be used as wiring. Therefore, development for reducing resistance by inserting an interlayer substance between layers of the multilayered graphene (intercalation) has been performed. Intercalation itself is a technique which has been studied widely for graphite for thirty years or more. Many interlayer substances are known, and an effect of reducing resistance by the interlayer substances has been indicated. However, when this intercalation is applied to a graphene having a fine width, doping strength is lowered with fining, and an effect of reducing resistance cannot be obtained disadvantageously. In addition, a graphene formed by low temperature CVD or the like required for integration has a difficulty in obtaining sufficient doping strength independent of a line width, disadvantageously.